As the working frequency of devices increases the effects of the IC package parasitics like reflection (caused by impedance mismatch) high frequency resonances and crosstalk among pins and bond wires becomes important. Accurate system simulation requires accurate modeling of these parasitics. Suitable circuit models are required to account for the effects of passive devices including packaging. Using a process called package modeling CMC has developed such circuit models and the document available for download below describes how these models were obtained. The document is intended as background material to accompany the models provided in the CMC-supported Cadence design kits. It provides the reader with information on:
1. The methods used to develop the lumped models
2. The reasons for choosing specific methods
3. Any limitations of the models
All CMC Microsystem account holders with a Prototyping or Designer Subscription are authorized to access this information. For more information contact Linda Dougherty at email@example.com or 613-530-4787.