Design Kit: TSMC 0.35 µm CMOS Process

Design Kit: TSMC 0.35 µm CMOS Process
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This design kit is for the 0.35µm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) and includes TSMC cell libraries.

This technology developed by TSMC and provided through CMC's partnership with MOSIS, is a 0.35µm dual poly 4 metal polycide CMOS process. The recommended nominal supply voltage is 3.3 volts. The design kit is suitable for analog mixed-signal and RF designs.

The minimum drawn gate length for this technology is: 0.35 µm.

Licensing Requirements or Restrictions

All CMC Subscribers are authorized to access this technology. Contact the Licensing Administrator at or 613-530-4787 for more information.

Acknowledging CMC

If your research benefits from products and services provided by CMC Microsystems, please acknowledge this support in any publications about your work. For more information, please visit Acknowledge CMC.