Application Note: Schematic and Post-Layout HSPICE Simulation for STMicroelectronics 90-nanometre CMOS Process

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Instructions on performing HSPICE simulation of a simple CMOS inverter drawn at the schematic level

Application Note: Schematic and Post-Layout HSPICE Simulation for STMicroelectronics 90-nanometre CMOS Process

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Product Details

Description

Product Description

Prepared by:

  • Ted Obuchowicz, VLSI/CAD Specialist, ECE, Concordia University, and
  • Frank Bernardo, PhD Candidate, ECE, Concordia University.

 

This application note is intended for researchers who wish to perform full-custom design with the design kit developed by STMicroelectronics for that company’s 90-nanometre CMOS process. This document provides instructions on performing HSPICE simulation of a simple CMOS inverter drawn at the schematic level. By following the instructions, you can create the corresponding layout of the inverter, perform a design rule check, layout versus schematic, obtain an extracted view and finally, and conduct a simulation of this extracted view.

 

All CMC Microsystem account holders with a Prototyping or Designer Subscription are authorized to access this application note. For more information contact Linda Dougherty at licensing@cmc.ca or 613-530-4787.

Support

Support Information
Product Specialist:
Version:1.0
Status:Released
Introduction Date:June 2, 2009
Last Updated:April 11, 2018
Support Level:Information Only
Delivery Method:CMC Download
Client Access:CMC Download