Application Note: Measuring Power Consumption of RTL Designs Based on Switching Activity Simulations

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Calculation of the dynamic and leakage power consumption of VHDL-based designs based on their switching activities

Application Note: Measuring Power Consumption of RTL Designs Based on Switching Activity Simulations

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Product Details

Description

Product Description

Prepared by Haytham Elmiligi, Ph.D. Candidate, Electrical and Computer Engineering Department, University of Victoria, BC, Canada.

 

This application note provides a step-by-step guide on calculation of the dynamic and leakage power consumption of VHDL-based designs based on their switching activities. It is supported by tips, codes, and instructions necessary to perform the experiment accurately using Synopsys® SYNOPSYS2005.09 (Design Compiler TM, VHDLSIM TM, and Power Compiler TM tools) for TSMC's 0.18-micron CMOS (CMOSP18) technology. This application note can also be used for other technologies if the library paths in the setup files are changed to appropriate libraries.

 

The intended users of this application note are the researchers who need a quick and easy-to-do method to estimate, measure, and compare the power consumption of their designs when various target technologies are considered.

 

All CMC Microsystem account holders with a Prototyping or Designer Subscription are authorized to access this application note. For more information contact Linda Dougherty at licensing@cmc.ca or 613-530-4787.

 

Support

Support Information
Product Specialist:
Version:1.0
Status:Released
Introduction Date:August 19, 2009
Last Updated:April 11, 2018
Support Level:Information Only
Delivery Method:CMC Download
Client Access:CMC Download