Application Note: Sourcing and Design Considerations for Incorporating Through-Silicon Via on a Wafer-Scale Integrated Circuit
Key steps to add a Through Silicon Via (TSV) and extra metal layers to a Complementary Metal Oxide Semiconductor (CMOS) wafer
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Prepared by Moufid Radji, Master of Engineering Candidate, McGill University, under co-supervision of Ricardo Izquierdo (UQÀM) and Anas A. Hamoui (McGill), and the DreamWafer® Research Team.
This application note outlines key steps to add a Through Silicon Via (TSV) and extra metal layers to a Complementary Metal Oxide Semiconductor (CMOS) wafer. This TSV process is described in relation to the fabrication of 200 mm Development Wafers for a WaferBoardTM product which is used for rapid system prototyping.
All CMC Microsystem account holders with a Prototyping or Designer Subscription are authorized to access this application note. For more information contact Linda Dougherty at firstname.lastname@example.org or 613-530-4787.
|Introduction Date:||July 16, 2010|
|Last Updated:||April 11, 2018|
|Support Level:||Information Only|
|Delivery Method:||CMC Download|
|Client Access:||CMC Download|