Application Note: ST 65nm LVS—Reconciling Extracted and Schematic Netlists

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Instructions on using Layout Versus Schematic (LVS) flow and the ST Microelectronics 65nm design kit

Application Note: ST 65nm LVS—Reconciling Extracted and Schematic Netlists

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Product Details

Description

Product Description

Prepared by Mike Bichan, Department of Electrical and Computer Engineering, University of Toronto, in co-operation with CMC Microsystems.

This document provides advice on using Layout Versus Schematic (LVS) flow and the ST Microelectronics 65nm design kit.

 

All CMC Microsystem account holders with a Prototyping or Designer Subscription are authorized to access this application note. For more information contact Linda Dougherty at licensing@cmc.ca or 613-530-4787.

Support

Support Information
Product Specialist:
Version:1.0
Status:Released
Introduction Date:August 26, 2009
Last Updated:April 11, 2018
Support Level:Information Only
Delivery Method:CMC Download
Client Access:CMC Download