Application Note: ST 65nm LVS—Reconciling Extracted and Schematic Netlists
Instructions on using Layout Versus Schematic (LVS) flow and the ST Microelectronics 65nm design kit
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Prepared by Mike Bichan, Department of Electrical and Computer Engineering, University of Toronto, in co-operation with CMC Microsystems.
This document provides advice on using Layout Versus Schematic (LVS) flow and the ST Microelectronics 65nm design kit.
All CMC Microsystem account holders with a Prototyping or Designer Subscription are authorized to access this application note. For more information contact Linda Dougherty at email@example.com or 613-530-4787.
|Introduction Date:||August 26, 2009|
|Last Updated:||April 11, 2018|
|Support Level:||Information Only|
|Delivery Method:||CMC Download|
|Client Access:||CMC Download|