Application Note: Design and Fabrication of a VI-CMOS Image Sensor
The design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding.
Minimum Subscription Required:
This application note starts with a motivation for vertical stacking of integrated circuits, focusing on the benefits for electronic image sensors. Next, it considers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a silicon die with CMOS circuits and a transparent die with photodetectors. As a specific example, the note presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. Finally, recommendations are made for future projects of a similar nature.
All CMC account holders with a Prototyping or Designer Subscription are authorized to access this product. For more information contact Linda Dougherty at firstname.lastname@example.org or 613-530-4787.
|Introduction Date:||August 6, 2010|
|Last Updated:||April 11, 2018|
|Support Level:||Information Only|
|Delivery Method:||CMC Download|
|Client Access:||CMC Download|