Application Note: Top-Down Approach to Design and Simulate Mixed-Signal Chips Using VerilogA/Schematic/Layout Representation
A top-down approach to designing mixed-signal microelectronic chips using Cadence Spectre Simulator from Cadence Design Systems, Inc.
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Prepared by Marco Macedo, M.Eng. Candidate, ECE, McGill University, in co-operation with CMC Microsystems.
This application note explains a top-down approach to designing mixed-signal microelectronic chips using Cadence Spectre Simulator from Cadence Design Systems, Inc. (http://www.cadence.com). This approach employs the VerilogA language used to model analog and digital circuits.
All CMC Microsystem account holders with a Prototyping or Designer Subscription are authorized to access this application note. For more information contact Linda Dougherty at email@example.com or 613-530-4787.
|Introduction Date:||February 24, 2011|
|Last Updated:||April 11, 2018|
|Support Level:||Information Only|
|Delivery Method:||CMC Download|
|Client Access:||CMC Download|