Application Note: Physical Design Flow and Techniques for Layout of Wafer-Scale Circuit with Through-Silicon Vias

Access Requirements

This application note describes a design flow for wafer-scale circuit with through-silicon vias.

Application Note: Physical Design Flow and Techniques for Layout of Wafer-Scale Circuit with Through-Silicon Vias

Minimum Subscription Required: Research

Buy a Subscription  to connect with information, tools, services and price discounts not otherwise available.

Product Details

Description

Product Description

Prepared by:

  • Yvon Savaria, Professor, Department of Electrical Engineering Department, École Polytechnique de Montréal
  • Yves Blaquière, Professor, Département d'informatique, Faculté des sciences, UQAM
  • Walder Andre, Postdoctoral Fellow, Department of Electrical Engineering Department, École Polytechnique de Montréal;

in co-operation with CMC Microsystems.

 

This application note describes a design flow for wafer-scale circuit with through-silicon vias. It addresses a number of design aspects including power planning, place & route, and TSV black-box handling. It also identifies the CAD tools required.

 

All CMC Microsystem account holders from a member university with a Prototyping or Designer Subscription are authorized to access this application note. For more information contact Linda Dougherty at licensing@cmc.ca or 613-530-4787.

Support

Support Information
Product Specialist:
Version:1.0
Status:Released
Introduction Date:September 23, 2011
Last Updated:April 11, 2018
Support Level:Information Only
Delivery Method:CMC Download
Client Access:CMC Download