Conference Presentation: DFT Methodology for 3D Stacked Microchips

Conference Presentation: DFT Methodology for 3D Stacked Microchips
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Prepared by Jeet Narsinghani, Digital Systems Engineer, CMC Microsystems.

This presentation describes design solutions for stacked microchips that address testability constraints through a design for test (DFT) approach. CMC is currently partnering with MOSIS and CMP to give researchers access to 3D microelectronic chip fab technology using the Tezzaron FaStack process. As part of their initial fabrication run using this technology, CMC is developing a reference design of a mixed signal system that describes the design flow and illustrates the incorporation of DFT features that add testability to the 3D structure. We aim to deliver design resources to academic researchers who wish to ensure testability in their microsystem prototypes incorporating stacked microchips.

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