User Guide: Debugging FPGA-based RTL Design Using Tektronix Certus (ICI-312)
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This document describes how to debug complex RTL level source code efficiently using Tektronix Certus. The tool is used to debug and verify a FPGA or ASIC design implemented in multi-FPGA platform.
The main advantage of this tool is that the designers do not need to re-synthesize the project when a new set of signals are analyzed. The design includes an embedded logic analyzer that captures all the necessary signals and gives full visibility to the design. This user guide demonstrates the debug capabilities of the Certus tool targeting the Xilinx ML605 development platform.
The guide provides a step-by-step instructions to:
- Add Certus cores to an existing RTL design using Certus Implementor.
- Implement the design in a Xilinx FPGA.
- Analyze the design using Certus Analyzer.
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