Advanced CMOS ESD IO Design: Application Note, Design Guidelines, and ST 28nm CMOS Bulk LP IO Library
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This product includes design guidelines and a custom‐developed ESD IO library using the ST 28nm LP bulk CMOS technology. The user manual introduces the dimensional and functional specifications of the provided IO cells that can be used as a reference or further customized based on the specific requirements. The design guideline document describes the general ESD protection schemes and the scheme used in the reference library.
- The ESD IO design methodology document – application note and design guidelines
- The ST 28nm LP bulk CMOS ESD IO library package
- Design guidelines & ESD design principles
- Digital & analog ESD IO cells
- Full schematics & layouts of the ESD IO cells
- IO supply cells in standard frame
- Wirebond pad cells, can be used as a reference to adapt to flip‐chip
- Low power bulk ST 28nm CMOS process option
- Distributed ESD network scheme
Licensing Requirements or Restrictions
You may access this technology if your university site has signed the STMicroelectronics Non Disclosure Agreement. To find out if your university has signed this agreement, see the STMicroelectronics University List.
In addition to the NDA, access to the PDK is subject to the Network Security Requirements.
For more information contact our Licensing Administrator at email@example.com or 613-530-4787.
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