Tutorial Guide: Using Mentor Tessent Tool for Scan-Based DFT Flow (ICI-331)
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This tutorial guide describes how to use the Tessent tool suite to create a scan-based DFT design for CMOSP13 technology. In this tutorial, the IBM 0.13-µm kit, Mentor Graphics’ Tessent, Synopsys synthesizer, and Cadence simulation tools are used. Using a design example, this tutorial demonstrates a scan-based DFT flow starting from an RTL simulation, followed by design synthesis, gate-level simulation, scan insertion, test-pattern generation, and verification. Using this example as a starting point, you can customize the environment settings and scripts file to build your own scan-based DFT circuitry for the CMOSP13 technology.
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