Tutorial Guide: Using Mentor Tessent Tool for Scan-Based DFT Flow (ICI-331)

Tutorial Guide: Using Mentor Tessent Tool for Scan-Based DFT Flow (ICI-331)
Minimum Subscription Required:
Price with Subscription

How to access this item?


This tutorial guide describes how to use the Tessent tool suite to create a scan-based DFT design for CMOSP13 technology. In this tutorial, the IBM 0.13-µm kit, Mentor Graphics’ Tessent, Synopsys synthesizer, and Cadence simulation tools are used. Using a design example, this tutorial demonstrates a scan-based DFT flow starting from an RTL simulation, followed by design synthesis, gate-level simulation, scan insertion, test-pattern generation, and verification. Using this example as a starting point, you can customize the environment settings and scripts file to build your own scan-based DFT circuitry for the CMOSP13 technology.

Licensing Requirements or Restrictions

All CMC Microsystem account holders with a Professor Research Subscription are authorized to access this document. For more information, contact our Licensing Administrator at licensing@cmc.ca or 613-530-4787.

Related Product

Acknowledging CMC

If your research benefits from products and services provided by CMC Microsystems, please acknowledge this support in any publications about your work. For more information, please visit Acknowledge CMC.