Quick Start Guide: 2nd Generation Acceleration Platform Development System (HP Z840 Altera-based) (ICI-334)

Quick Start Guide: 2nd Generation Acceleration Platform Development System (HP Z840 Altera-based) (ICI-334)
Minimum Subscription Required:
Designer
Price with Subscription
$0.00

How to access this item?

Contact Us

Need help? Any feedback?

Please email us at: docs@cmc.ca.

Description

This quick start guide provides information about the default configuration provided by CMC for the emSYSCAN Acceleration Platform running an Altera field-programmable gate array (FPGA). The Acceleration Platform is running CentOS 6.8 and has all of the tools to get started with the Altera OpenCL SDK tools.

The FPGA board installed in this is system is the Nallatech 385A, which is a high performance reconfigurable x8 PCIe form factor board using the Altera Arria 10 FPGA. This board features:

  • Low Profile PCIe form factor
  • Arria 10 1150 GX FPGA with up to 1.5 TFlops
  • Network Enabled with (2) QSFP 10/40 GbE Support
  • 8 GB DDR3 on-card memory
  • PCIe Gen3 x8 Host Interface
  • OpenCL tool flow
    • Open, royalty-free unified programming model
  • Network interfaces
    • Support for multiple line rates and protocols

Licensing Requirements or Restrictions

All CMC Microsystem account holders with a Professor Research Subscription are authorized to access this document. For more information, contact our Licensing Administrator at licensing@cmc.ca or 613-530-4787.


Acknowledging CMC

If your research benefits from products and services provided by CMC Microsystems, please acknowledge this support in any publications about your work. For more information, please visit Acknowledge CMC.