Design Methodology: STMicroelectronics 28nm FD-SOI CMOS Technology Digital/Mixed-Mode Design Flow
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Authored by Shayan Shahramian, Tony Chan Carusone, both from the Department of Electrical and Computer Engineering, University of Toronto; in Collaboration with CMC Microsystems.
This document outlines the Digital/Mixed Mode design flow for STMicroelectronics' 28nm FD-SOI CMOS technology:
- Section 2 includes setting up the standard cell libraries and appropriate models for 28nm STM FD-SOI. Initialization commands are provided for Design Vision which is used for the design synthesis.
- Section 3 outlines the initialization of encounter and setting up the correct libraries for place & route. Section 3 includes generating a GDS le and post place & route verilog to be imported into Virtuoso Cadence.
- Section 4 outlines importing the design and the blackbox LVS process for Virtuoso Cadence.
- Finally, section 5 shows the process for performing mixed-mode simulations.
Table of Contents
- Design Synthesis in Design Vision
- Design Place & Route in Encounter
- Importing Design into Virtuoso Cadence
- LVS Procedure for Black Box Standard Cells
- Mixed-Mode Simulations
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