Reference Design and Design Methodology: Design of Silicon Interposers Using Standard CMOS Technologies
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To increase the IO density and aggregate bandwidth between multiple chips, researchers have started looking at 2.5D and 3D integration to put the integrated circuits as close as possible. In these new technologies, multiple chips are placed inside one package and they can communicate with each other through the packaging substrate. The packaging substrate that is used to build interconnects between the chips and also to the board is usually called interposer. Different types of materials may be used to build an interposer, but Silicon, glass, and organic are the most popular ones. Among these materials, silicon has gained a lot of interests because it is the same material that is being used to fabricate integrated circuits. Therefore, the silicon interposers can be fabricated by customizing the regular CMOS process employed by different CMOS technologies and it can achieve the highest resolution and density in comparison with organic or glass interposers.
The included document is intended as an introduction to the design of silicon interposers using standard CMOS technologies. Throughout this document, AMS 0.35 µm CMOS – standard process is used as our reference, but the materials provided here may be applied to any other CMOS technologies. The rest of the document is organized as follows:
- Section 2 explains the design and verification of silicon interposers.
- Section 3 describes the interconnect modeling.
- Section 4 covers the characterization of silicon interposers.
- Section 5 discusses the packaging of silicon interposers.
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This product requires access to AMS 0.35-μm CMOS technology. Access to this technology is based on a site license. Each institute (e.g., university) is required to get licensed and multiple researchers can access the technology. Check with your STC Administrator (see the List of STC Administrators
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- Foundry: austriamicrosystems Process: C35B4C3, C35B4O1, H35B4D3
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