CAD: Xilinx SDAccel

CAD: Xilinx SDAccel
Minimum Subscription Required:
Research

Description

The SDAccel™ development environment for OpenCL™, C, and C++, enables up to 25X better performance/watt for data center application acceleration leveraging FPGAs. SDAccel, member of the SDx™ family, combines the industry's first architecturally optimizing compiler supporting any combination of OpenCL, C, and C++ kernels, along with libraries, development boards and the first complete CPU/GPU like development and run-time experience for FPGAs.


First Architecturally Optimizing Compiler for OpenCL, C, and C++

  • Architecturally optimizing compiler delivers up to 25X better performance/watt compared to CPU/GPU
  • Delivers 3X the performance and resource efficiency of other FPGA solutions
  • Enables new or existing OpenCL, C and C++ code for creating high performance accelerators

First Complete CPU/GPU-Like Development Experience on FPGAs

  • First complete software development environment targeting FPGAs
  • Optimize applications on FPGA platforms with little to no FPGA experience
  • Easily migrate applications to FPGAs while maintaining and reusing OpenCL, C and C++ code

First complete CPU/GPU-Like Run-time Experience on FPGAs

  • Supports large applications with multiple programs and CPU/GPU-like on-demand loadable compute units
  • Maintains system functionality during program transitions and keeps critical system interfaces and functions live during application execution

The SDAccel development environment allows FPGA accelerators to be shared across multiple applications using on-the-fly compute unit reconfiguration.

 

Technical Details

Software Version 2018.3
Operating System Linux (RHEL 7.4-7.5 or CentOS 7.4-7.5)
Bit Level 64-bit
Software Access Download from CMC Microsystems
Software Access Key
Support CMC Microsystems

 

What You Get

  • Faculty: receives a pass that allows you, your students and your research staff to access Xilinx SDAccel.
  • Access is to a shared license pool.
  • One pass supports multiple simultaneous users from your research group, up to the limits of the available licenses in the shared pool.
  • Access for one year

 

Documentation 

Licensing Requirements or Restrictions

  • Use of this design tool is restricted to university research only.
  • Access to the software license keys are limited to clients, their graduate students and research staff.
  • Any NDN university Designer or Prototyping subscriber is authorized to access this product.

For more information, contact the Licensing Administrator at 613-530-4787 or licensing@cmc.ca.


Acknowledging CMC

If your research benefits from products and services provided by CMC Microsystems, please acknowledge this support in any publications about your work. For more information, please visit Acknowledge CMC.