Quick Start Guide: 2nd Generation Acceleration Platform Development System (HP Z840 Xilinx-based) (ICI-347)

Quick Start Guide: 2nd Generation Acceleration Platform Development System (HP Z840 Xilinx-based) (ICI-347)
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Description

This quick start guide provides information about the default configuration provided by CMC for the emSYSCAN Acceleration Platform running a Xilinx field-programmable gate array (FPGA) for OpenCL development. The Acceleration Platform is running CentOS 6.8 and has all of the tools to get started with the SDAccel platform.

The FPGA board installed in this is sytem is the XIL-ACCEL-KU115, which is a high performance reconfigurable x16 PCIe form factor board using the Xilinx KU115 FPGA. This board features:

  • Connectivity to the host computer uses the Xilinx DMA Subsystem for PCI Express (PCIe), containing a Scatter Gather DMA and PCI Express 3.x Integrated Block. The Xilinx Developer Board for Acceleration with KU115 supports Gen3 x8 connectivity. * Four UltraScale Memory IP instances enable access to available DDR4 SDRAM. The Xilinx Developer Board for Acceleration with KU115 board contains four channels of DDR4-2400 SDRAM, at 4GB per channel for a total of 16GB global memory.
  • AXI SmartConnect IP provides high-performance AXI Memory Mapped connectivity among IP cores throughout the platform.
  • The SDAccel OpenCL Programmable Region IP core and its designated level of hierarchy enable the platform to be used with the SDAccel System Compiler and C/C++, OpenCL, and RTL user kernels.
  • Partitioning, clocking, and reset networks are designed to support the expanded partial reconfiguration flow, including two independent frequency-adjustable kernel clock sources.
  • Support for SDx Environments application profiling via trace offload hardware infrastructure, and for flash memory programming via SPI flash IP infrastructure.

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Acknowledging CMC

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