Fab: Open-Gate Silicon JFET (OG Si-JFET)


Silicon Junction Field Effect Transistors are fabricated at 3IT.Nano and delivered with an open upper gate for integration of solution-processed functional materials. The platform is useful for the study and optimization of novel hybrid material systems in silicon and the realization of high-performance CMOS-compatible detectors.


  • Upper JFET gates open to ambient, ready for post-processing
  • Micro-sized, high mobility (µ > 100 cm2/Vs), low-voltage silicon JFET
  • Die size 14 mm × 16 mm (baseline process for use with optional test fixture); minimum size 5 mm x 5 mm


Note:The expected number of chips to be delivered for this technology is multiples of 5 (for baseline process and die size 14 mm × 16 mm).


Process Summary

  • 4-mask process on epitaxial Si with 5 µm feature size
  • Front- and back-side Boron ion implantation
  • Aluminum-silicon metallization
  • SiN passivation
  • Backside gate


Example Applications

  • Optical detection using quantum dots, perovskites, nanostructured semiconductors, organic molecules and polymers
  • Biomarker detection using immobilized probes



  • Cloud design environment (includes process design documents, layout template, reference design and simulation for IR light detector using quantum dots)
  • Test fixture with ports for optical input and gas ambient control
  • DRC and engineering support for OG Si-JFET design
  • Sub-dicing (optional)


Licensing Requirements or Restrictions

Use of design materials is subject to the usage terms and conditions set out in the License Grant.

Acknowledging CMC

If your research benefits from products and services provided by CMC Microsystems, please acknowledge this support in any publications about your work. For more information, please visit Acknowledge CMC.