Design Kit: Open-Gate Silicon JFET (OG Si-JFET) in L-Edit and Synopsys Sentaurus

Design Kit: Open-Gate Silicon JFET (OG Si-JFET) in L-Edit and Synopsys Sentaurus
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Description

Silicon Junction Field Effect Transistors are fabricated at 3IT.Nano and delivered with an open upper gate for integration of solution-processed functional materials. The platform is useful for the study and optimization of novel hybrid material systems in silicon and the realization of high-performance CMOS-compatible detectors.

Features

  • Micro-sized, high mobility (m > 1000 cm2/V) low-voltage silicon JFET
  • Upper JFET gates open to ambient, ready for post-processing
  • Optional test fixture with ports for optical and gas

Services

  • Cloud design environment (includes process design documents, layout template, reference design and simulation for IR light detector using quantum dots)
  • DRC and engineering support for OG Si-JFET design

Licensing Requirements or Restrictions

Use of design materials is subject to the usage terms and conditions set out in the License Grant.


Acknowledging CMC

If your research benefits from products and services provided by CMC Microsystems, please acknowledge this support in any publications about your work. For more information, please visit Acknowledge CMC.