Explore and develop custom processors and hardware accelerators for ASIC and FPGA demonstration using industrial-grade tools. Synopsys' ASIP Designer is a tool suite that enables rapid design and implementation of Application-specific instruction-set processors (ASIPs), achieving high performance and low power, while maintaining software programmability.
ASIP Designer is available for research and training; however, to ensure appropriate and successful use of the tool, access must be approved in advance. Please contact firstname.lastname@example.org for details and to initiate your request. On approval, CMC will provide:
- License access
- Engineering technical support (getting started and continuing use)
About ASIP Designer
Synopsys’ ASIP Designer is a tool suite that brings ASIP design within easy reach. Key capabilities include:
- Rapid exploration of architectural choices,
- Generation of an efficient C/C++-compiler based software development kit, and
- Automatic generation of power and area-optimized synthesizable RTL.
ASIP Designer's patented technology supports the following features:
- Modeling of ASIP instruction-set architectures in the nML processor description language. nML is a high-level definition language for describing a processor architecture and instruction set (ISA). nML offers designers the abstraction level of a programmer's manual of a processor. Also, with nML the ASIP’s periphery can be modeled in a cycle- and bit-accurate way. nML offers unprecedented architectural breadth, enabling IP development for almost any vertical market.
- Unique compiler-in-the-loop technology, enabled by the automatic generation of a comprehensive software development kit (SDK) for each ASIP modeled in nML, containing the following components:
- An optimizing compiler, recognized for its efficient code generation and quick and automatic retargetability to new ASIP architectures. The compiler supports C (optionally extended with user-defined data types and operators using C++ classes and function overloading), C++, and OpenCL C (OpenCL kernel language). The compiler can cope well with architectural peculiarities of DSP cores. It supports instruction-level and data-level parallelism, deeply pipelined instructions, specialized arithmetic functions, custom data-types, specialized address generation units, heterogeneous register structures, and various degrees of instruction encoding (ranging from VLIW to highly encoded instruction sets).
- A linker that builds an executable file from separately compiled Elf/Dwarf object files for different C functions.
- An assembler and disassembler that translates machine code from assembly into binary format and back.
- A fast instruction-set simulator, offering both cycle-accurate and instruction-accurate abstraction levels generated from the same nML model, and easy integration into cycle-accurate and transaction-level virtual prototypes.
- A flexible (multicore) debugger, which can be used in connection to both instruction-set simulators and on-chip debug hardware (via JTAG).
- Multi-faceted profiling capabilities to analyze the instruction-set architecture for hot-spots and to drive the architectural optimization process.
- Automatic generation of a power and area efficient hardware implementation of each ASIP, in synthesizable Verilog or VHDL. A JTAG interface and a debug controller can optionally be generated, to support on-chip debugging. Generated HDL code can be fed into supported ASIP and FPGA prototyping flows using Synopsys Design Vision (ASIC synthesis) or Synopsys Synplify (FPGA synthesis).
- Multi-faceted verification capabilities, including the automatic generation of ASIP-specific test programs in C and assembly code.
ASIP Designer comes with a wide range of example ASIP designs, with highly differentiating architectures provided in nML source code. This enables designers to quickly start to create their own ASIP targeting their specific application requirements.
More details on ASIP Designer can be found at https://www.synopsys.com/dw/ipdir.php?ds=asip-designer.
What You Get
- Faculty: receive a pass that allows you, your students, PDFs, and research staff participating in your project to access Synopsys ASIP Designer.
- Access is to a shared license pool.
- One pass supports multiple simultaneous users from your project research group, up to the limits of the available licenses in the shared pool.
- Access for one year