Other Microelectronics Make Application Notes

Name Summary
Application Note: Silicon Etching Process Using Laser Milling Techniques This application note proposes a silicon etching process based on a laser milling technique as an alternative to the reactive ion etching (RIE) process that is commonly use to etch and release silicon structures.
Application Note: Characterization of Anisotropic Conductive Film Based on Vertical Fibers for Post-CMOS Wafer-Level Packaging This product is an application note capturing the use of anisotropic conductive film in a wafer-level prototype.
Application Note: Low Temperature Co-Fired Ceramic Design Flow The application note demonstrates the design flow for LTCC technology.
Application Note: Small Die Handling for Post-Processing using ICP-DRIE Description of a series of microfabrication steps aimed at handling and post-processing a small complementary metal–oxide–semiconductor (CMOS) die
Application Note: Silicone Encapsulation of Mechanically Flexible Multilayer Integrated System on Polymer Substrate for Medical Applications Description of a set of basic guidelines for encapsulating small electronic components on multilayered mechanically flexible polymer substrates
Application Note: Preparing and Exporting Ansoft Designer Layout Files for Use with T-Tech IsoPro Milling Software Procedures to prepare and export Ansoft Designer Planar EM layouts to an intermediate format compatible with most milling software
Application Note: Guidelines for Designing Printed Circuit Boards Using Polyimide Materials Summary of CMC’s experiences and insights in the use of polyimide (FLEX) materials for printed circuit boards (PCBs)
Application Note: Assembly of a Compact Fluorescence Detection/Imaging System to Detect Biological Materials Description of a compact fluorescence detection/imaging system for detecting biological materials
Application Note: Addition of Microelectrode Arrays on CMOS Die Using Gold Stud Bumping for Neural Interfacing Applications Description of adding microelectrode arrays on CMOS die using gold stud bumping for neural interfacing applications
Application Note: A Procedure for Mounting Loose Integrated Circuit Die on a Non-Conductive Glass Substrate Description of a technique for directly mounting loose integrated circuit (IC) die on a non-conductive glass surface
Application Note: Post-Processing Techniques to Address Challenges in Die Handling; Mask Alignment; and Edge Bead Infringement Description of techniques to prepare individual semiconductor die for post processing