Microelectronics Design Application Notes

Name Summary
Application Note: Setting up EMX 6-Virtuoso Interface This application note provides instructions to integrate EMX 6 into Cadence Virtuoso.
Application Note: Creating a Mask File for TCAD Simulation Using Synopsys IC WorkBench A Graphical Database System (GDS) layout file generated by a third-party CAD tool is imported into Synopsys IC WorkBench. After it is imported, it is adapted and saved in a way that is recognized for use by Synopsys Sentaurus Process.
Application Note: Adding Package Libraries to a Cadence Allegro PCB Design XL Project Procedures to add library of CMC supported packages to Cadence Allegro PCB Design XL Project
Application Note: Inter-Reticle Stitching Rules and Constraints for a Wafer-Scale Integrated Circuit This application note describes inter-reticle stitching rules and constraints for a wafer-scale integrated circuit.
Application Note: Physical Design Flow and Techniques for Layout of Wafer-Scale Circuit with Through-Silicon Vias This application note describes a design flow for wafer-scale circuit with through-silicon vias.
Application Note: Top-Down Approach to Design and Simulate Mixed-Signal Chips Using VerilogA/Schematic/Layout Representation A top-down approach to designing mixed-signal microelectronic chips using Cadence Spectre Simulator from Cadence Design Systems, Inc.
Application Note: Using Synopsys Sentaurus to Simulate a P-N Junction This application note describes the use of the Sentaurus software by presenting a simple and practical application: modeling and simulating a Gallium Arsenide (GaAs) p-n junction.
Application Note: Developing Miniature Power Blocks Attached to Wafer-Scaled IC This application note describes the development of miniature power blocks for a wafer-scale IC.
Application Note: Design and Fabrication of a VI-CMOS Image Sensor The design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding.
Application Note: Mixed Fluid-Heat Transfer for Thermal Modeling and Analysis of a Wafer-Scale Integrated Circuit Description of a mixed fluid-heat transfer approach for thermal modeling and thermal analysis
Application Note: Sourcing and Design Considerations for Incorporating Through-Silicon Via on a Wafer-Scale Integrated Circuit Key steps to add a Through Silicon Via (TSV) and extra metal layers to a Complementary Metal Oxide Semiconductor (CMOS) wafer
Application Note: ST 65nm LVSā€”Reconciling Extracted and Schematic Netlists Instructions on using Layout Versus Schematic (LVS) flow and the ST Microelectronics 65nm design kit
Application Note: Setting Current EDA Tools to Interpret Design Kits Created for Older EDA Tool Versions Guidance on migrating older digital design kits to accommodate currently supported synthesis and placement and routing tools
Application Note: Simulating Air-Bridges of CPFC GaN MMIC in Momentum A method to model air-bridges in The Canadian Photonics Fabrication Centre (CPFC) GaN MMIC process