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Application Note: Setting up EMX 6-Virtuoso Interface
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This application note provides instructions to integrate EMX 6 into Cadence Virtuoso.
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Application Note: Creating a Mask File for TCAD Simulation Using Synopsys IC WorkBench
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A Graphical Database System (GDS) layout file generated by a third-party CAD tool is imported into Synopsys IC WorkBench. After it is imported, it is adapted and saved in a way that is recognized for use by Synopsys Sentaurus Process.
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Application Note: Adding Package Libraries to a Cadence Allegro PCB Design XL Project
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Procedures to add library of CMC supported packages to Cadence Allegro PCB Design XL Project
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Application Note: Inter-Reticle Stitching Rules and Constraints for a Wafer-Scale Integrated Circuit
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This application note describes inter-reticle stitching rules and constraints for a wafer-scale integrated circuit.
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Application Note: Physical Design Flow and Techniques for Layout of Wafer-Scale Circuit with Through-Silicon Vias
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This application note describes a design flow for wafer-scale circuit with through-silicon vias.
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Application Note: Top-Down Approach to Design and Simulate Mixed-Signal Chips Using VerilogA/Schematic/Layout Representation
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A top-down approach to designing mixed-signal microelectronic chips using Cadence Spectre Simulator from Cadence Design Systems, Inc.
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Application Note: Using Synopsys Sentaurus to Simulate a P-N Junction
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This application note describes the use of the Sentaurus software by presenting a simple and practical application: modeling and simulating a Gallium Arsenide (GaAs) p-n junction.
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Application Note: Developing Miniature Power Blocks Attached to Wafer-Scaled IC
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This application note describes the development of miniature power blocks for a wafer-scale IC.
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Application Note: Design and Fabrication of a VI-CMOS Image Sensor
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The design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding.
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Application Note: Mixed Fluid-Heat Transfer for Thermal Modeling and Analysis of a Wafer-Scale Integrated Circuit
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Description of a mixed fluid-heat transfer approach for thermal modeling and thermal analysis
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Application Note: Sourcing and Design Considerations for Incorporating Through-Silicon Via on a Wafer-Scale Integrated Circuit
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Key steps to add a Through Silicon Via (TSV) and extra metal layers to a Complementary Metal Oxide Semiconductor (CMOS) wafer
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Application Note: ST 65nm LVS—Reconciling Extracted and Schematic Netlists
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Instructions on using Layout Versus Schematic (LVS) flow and the ST Microelectronics 65nm design kit
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Application Note: Setting Current EDA Tools to Interpret Design Kits Created for Older EDA Tool Versions
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Guidance on migrating older digital design kits to accommodate currently supported synthesis and placement and routing tools
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Application Note: Simulating Air-Bridges of CPFC GaN MMIC in Momentum
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A method to model air-bridges in The Canadian Photonics Fabrication Centre (CPFC) GaN MMIC process
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