Design Kit: TSMC 0.18 µm CMOS Process

Design Kit: TSMC 0.18 µm CMOS Process
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This technology, developed by the Taiwan Semiconductor Manufacturing Company (TSMC) and supplied through CMC's partnership with MOSIS, is a 0.18µm single poly six metal salicide CMOS process. The recommended nominal supply voltages are 1.8 and 3.3 volts. This kit supports design in the following areas: analog low power RF and full custom digital.

The minimum drawn gate length for this TSMC technology is 0.18 µm. The available process options are:

  • Logic (default)
  • Mixed Signal (deep N-well and metal-to-metal [MiM] capacitor)
  • Thick metal - 6

This kit should be installed in the Supported Technology Configuration (STC) environment supported by CMC. Only administrators of the STC disk at CMC's member universities may obtain the design kit from CMC's SFTP server, and install the kit at their university. Contact your STC Administrator for access, see the list of STC Administrators.

Licensing Requirements or Restrictions

All CMC Subscribers are authorized to access this technology. Contact the Licensing Administrator at or 613-530-4787 for more information.

Acknowledging CMC

If your research benefits from products and services provided by CMC Microsystems, please acknowledge this support in any publications about your work. For more information, please visit Acknowledge CMC.