Fab: TSMC 0.18 µm CMOS Process Technology

Fab: TSMC 0.18 µm CMOS Process Technology
Minimum Subscription Required:
Peer Reviewed Price for Canadian Academic
Price for Canadian Academics


Minimum charge is for a
1.1 x 1.1 mm2 design. Other design areas can be quoted upon request.


This 0.18-micron CMOS technology is offered with a robust design kit (with a commercial cell library) that supports RF, analog, mixed-signal and digital design flows, plus various tutorials that use this technology for the design example.

CMC’s multi-project wafer service delivers Taiwan Semiconductor Manufacturing Company (TSMC) nanometer and micron-scale CMOS technologies. 

The 0.18 µm CMOS (CMC term is CMOSP18) process is suitable for:

  • Analog circuits
  • Full custom digital circuits
  • RF circuits
  • Mixed-signal circuits

Process Details:

  • Electrical Contact Forming Technology:
    • Salicide
  • Layers:
    • 6 metal, 1 poly
  • Supply Voltages:
    • 1.8 V and 3.3 V
  • Minimum Drawn Gate Length:
    • 0.18 μm
  • Options:
    • Logic (default)
    • Mixed-signal (deep N-well and metal-insulator-metal [MiM] capacitor)
    • Thick metal

Note: The expected number of chips to be delivered for this technology is 40.


Licensing Requirements or Restrictions

Please see Help with Licensing to review licensing procedure. For more information, contact our License Administrator at licensing@cmc.ca or 613-530-4787.

Acknowledging CMC

If your research benefits from products and services provided by CMC Microsystems, please acknowledge this support in any publications about your work. For more information, please visit Acknowledge CMC.