Application Note: Top-Down Approach to Design and Simulate Mixed-Signal Chips Using VerilogA/Schematic/Layout Representation

Prepared by Marco Macedo, M.Eng. Candidate, ECE, McGill University, in co-operation with CMC Microsystems.

This application note explains a top-down approach to designing mixed-signal microelectronic chips using Cadence Spectre Simulator from Cadence Design Systems, Inc. (http://www.cadence.com).  This approach employs the VerilogA language used to model analog and digital circuits.

All CMC Microsystem account holders with a Prototyping or Designer Subscription are authorized to access this application note. For more information contact Linda Dougherty at licensing@cmc.ca or 613-530-4787.