Application Note: Physical Design Flow and Techniques for Layout of Wafer-Scale Circuit with Through-Silicon Vias

Prepared by:

• Yvon Savaria, Professor, Department of Electrical Engineering Department, École Polytechnique de Montréal
• Yves Blaquière, Professor, Département d'informatique, Faculté des sciences, UQAM
• Walder Andre, Postdoctoral Fellow, Department of Electrical Engineering Department, École Polytechnique de Montréal;

in co-operation with CMC Microsystems.

This application note describes a design flow for wafer-scale circuit with through-silicon vias. It addresses a number of design aspects including power planning, place & route, and TSV black-box handling. It also identifies the CAD tools required.

All CMC Microsystem account holders from a member university with a Prototyping or Designer Subscription are authorized to access this application note. For more information contact Linda Dougherty at licensing@cmc.ca or 613-530-4787.