Application Note: High Performance Design for Xilinx FPGAs

Prepared by Paul Leons with assistance from Hugh W. Pollitt-Smith, both from CMC Microsystems; and Samar Abdi from Concordia University.

This application note describes several strategies in Xilinx field programmable gate arrays (FPGAs) for optimizing the design and meeting timing requirements. The document also illustrates the features of the Xilinx PlanAhead software for high performance FPGA design.

This application note covers the following:

• Guidelines for Configuring Global Constraints
• FPGA Design Techniques
• Procedure for Analyzing the Timing Report and Design Rule Check (DRC) 
• Synthesis and Implementation Techniques
• Floorplanning Techniques

This application note is targeted to researchers who are interested in high performance system implementations for FPGA platforms and who have a sound knowledge of Digital Design, Hardware Description Language (HDL), and familiarity with the Xilinx ISE Design flow.

To perform the procedures, you must have Xilinx ISE Design Tool suite installed on a host PC.