Design Kit: Interposer Platform PDK for 2.5D Integration

Cost-effective, fast-turnaround manufacturing platform for 2.5D integration of heterogeneous chip technologies in a compact form factor. Supported by a comprehensive environment for design, manufacturing, and test of physical prototypes. Amenable to laboratory testability and field-trial demonstration. Developed in partnership with Innotime Technologies Inc.

Technology

• 400-μm thick silicon substrate with array of silver-filled Through Silicon Vias (TSVs) connecting top and bottom metal layers
• 3 customizable metal redistribution layers (RDLs) to route electrical signals between flip-chipped or wire-bonded die as well as off-the-shelf components such as SMT, SOIC or CSP
• ​Bottom metal layer can be used for routing or for mounting a standard ball grid contact array (BGA).
  
  

Design Environment

• Tanner L-Edit/S-Edit tools for design entry
• PDK supports standard design components and primitives, design and verification tasks (e.g., auto-routing, LVS and DRC) and output file formats such as GSDII for hand-off to manufacturing.
• Library of design footprints for adding off-the-shelf components
• Designers can quickly and easily place custom and/or off-the- shelf components on the interposer TSV array and customize the routing of electronics signals between the components and through to the back side BGA layer.
  
  

Test and Validation Infrastructure

• Prototypes can be mounted on breakout boards or ZIF sockets for interfacing to test equipment or hardware such as FPGA boards for device and system test, characterization and application development.
• Test and programmable hardware available through CMC Equipment Pool for short-term access.
• A test chip and test report demonstrates key parameters and operating constraints for this technology.
  
  

Available Now

• PDK V2.1
• User Guide
• Reference designs and training materials
• Tanner L-Edit/S-Edit design tools
• Engineering support
  
  

Coming Soon

• Interposer Manufacturing Service