3.4 De-Embedding Pad Parasitics

3.4 De-Embedding Pad Parasitics

This section is divided into the following subsections:

3.4.1 De-Embedding Procedure

3.4.1.1 Performing De-Embedding Calculations Using Matlab

3.4.1.2 Performing De-Embedding Calculations Using Libra

3.4.1.3 Procedure for Saving and Formatting Measurement Data

3.4.2 References

If you want to characterize the intrinsic DUT to model its behaviour or obtain device model parameters without the bond pads to embed the device in a larger IC, then some correction to the measurements must be applied to correct for the pad parasitics. This is because the associated parasitic admittances and impedances can otherwise overwhelm the intrinsic device S-parameters and limit device response bandwidth. The removal of additional pad parasitics may also be desirable when the transition on-wafer is dramatically different than that of the ISS such as on silicon substrates. In many cases, however, these transition errors may be de-embedded using simple lumped element equivalent circuit models.

The bond pad parasitics are a combination of shunt capacitances and resistances, due to the conductive substrate of Si ICs and series inductance and resistance of the input and output interconnect. To make an accurate measurement of the intrinsic DUT, two techniques are commonly used for de-embedding, with the first considered to be the most accurate [2]:

  1. Using ISS calibration and de-embedding structures

    Parasitic admittances (C-G) and/or impedances (R-L) in the DUT connections can be measured and later on removed by measuring extra test structures containing only the structures that represent the parasitic admittances or impedances with the DUT removed, and then running a pad parasitic removal routine that will subtract these measured parasitics from the device measurement data.

    An Impedance Standard Substrate, ISS, is first used in conjunction with the Vector Network Analyzer (VNA) to correct for the response of the probes and cables and bring the measurement reference plane to the probe tips. The ISS is typically low loss and contains shorts, trimmed 50 ohm loads, and thru connections to enable the operator to perform a Short, Open, Load, Thru (SOLT) calibration. Thus, the measurement will include pad parasitics and interconnect parasitics from interconnect emanating from the pad to the other devices on your substrate, as well as the device.

    To correct for the parallel RC parasitics of the pad structure, the S-parameters of the DUT (including its pads) and the S-parameters of the de-embedding structure ("open" dummy pads) are measured. The measurement data from both measurements are converted from S-parameters to Y-parameters and the admittance of the open pads is subtracted from the admittance of the DUT. Doing so effectively removes the pad parasitics. The "corrected" data is then converted back to S-parameters for further processing or plotting.

    The series RL parasitics can be subtracted by using a different test structure ("short" dummy pads) which uses the same metal as the test device, but has the metal shorted (ground and signal lines) in place of the test device. You follow the same measurement procedure as above but the subtraction is performed using Z-parameters instead of Y-parameters on either the corrected data (if both shunt and series parasitic correction is being made) or the raw DUT S-parameter data (if only series parasitics correction is being made).

    Normally the admittance correction is used for high impedance devices and the impedance correction is used for low impedance devices. However, both types of correction can be applied together.

    An equivalent lumped-element circuit representation of the de-embedding structure parasitics can be used for circuit computations and has been shown to be valid up to 18 GHz [5]

  2. Using on-chip calibration standards

    The second method is to calibrate the network analyzer using calibration standards (SOLT) which have been designed on chip with pads which mimic the parasitics of the DUT pads. This technique, however, has been shown to be less accurate than the above method [2].

Issues:

Pad effects will be negligible or easily subtracted from the measured data when the pads are small. Keep in mind that although the pads can be de-embedded from some measurements (e.g., S-parameter measurements), it will be difficult to do so for others (e.g., noise measurements and third-order intercept measurements) because of the equipment used.

When the measured Y-parameters of the dummy are large compared to the measured Y-parameters of the device, the corrected Y-Parameters become extremely sensitive to jitter in the measurement of the dummy. Also, variations in substrate resistivity and oxide thickness over the wafer can affect the dummy characteristics. Therefore, it is recommended that the dummy and the DUT be on the same die for easy tracking and improvement of measurement accuracy.

Measurement repeatability depends on the measurement instrument and fixturing and whether or not the dummy pads are equivalent to the DUT, both in terms of physical appearance and location on the wafer.


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