Application Note: Inter-Reticle Stitching Rules and Constraints for a Wafer-Scale Integrated Circuit

Prepared by:

• Yvon Savaria, Professor, Department of Electrical Engineering Department, École Polytechnique de Montréal
• Yves Blaquière, Professor, Département d'informatique, Faculté des sciences, UQAM
• Walder Andre, Postdoctoral Fellow, Department of Electrical Engineering Department, École Polytechnique de Montréal;

in co-operation with CMC Microsystems.

This application note describes inter-reticle stitching rules and constraints for a wafer-scale integrated circuit. It shows a process of reticle stitching and the design considerations of using such a stitching technique to create designs larger than the maximum reticle size.

All CMC Microsystem account holders from a member university with a Prototyping or Designer Subscription are authorized to access this application note. For more information contact Linda Dougherty at licensing@cmc.ca or 613-530-4787.