Application Note: Addition of Microelectrode Arrays on CMOS Die Using Gold Stud Bumping for Neural Interfacing Applications
Description of adding microelectrode arrays on CMOS die using gold stud bumping for neural interfacing applications
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Prepared by Ruslana Gelman, MSc Candidate, Applied Science and Engineering, University of Toronto.
This application note describes techniques for the following:
- A means of adding microelectrode arrays on CMOS die using gold stud bumping for neural interfacing applications
- Partial encapsulation for controlled die access
- An experimental setup for interfacing brain tissue with the fabricated neural CMOS microsystem
- An initial assessment of the efficacy of stacked stud bumps as neural recording electrodes
All CMC Microsystem account holders with a Prototyping or Designer Subscription are authorized to access this application note. For more information contact Linda Dougherty at email@example.com or 613-530-4787.
|Introduction Date:||October 30, 2008|
|Last Updated:||September 20, 2016|
|Support Level:||Information Only|
|Delivery Method:||CMC Download|
|Client Access:||CMC Download|